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Chapter: 11 -Problem: 4 >> The ac schematic of an amplifier is shown in Fig. 11.49. The circuit is fed from a current source iSand data are as follows:RS =1 k „¦ RL= 10 k „¦ IC = 1 mAβ = 50 rb = 0 ro = ˆžNeglecting capacitive effects and flicker noise, calculate the total noise voltage spectral density at vo in V2 /Hz. Thus calculate the MDS at iS if the circuit band-width is limited to a sharp cutoff at 2 MHz. Compare you
Answer Preview: Using 11 38 = 1 12 10 -12 V 2 /HZ If f = 2 MHZ 2 o…

, Chapter: 7 -Problem: 24 >> Replace the bipolar transistors in Fig. 7.40 with NMOS transistors. Repeat the calculations inProblem 7.21, using RS = 100 kΩ, RL = 3 kΩ, and the NMOS transistor model data in Problem 7.2, but use Cdb = 200 fF and Csb = 180 fF here. Take ID1 = 50 µA and ID2 = 1 mA.Data from Prob. 7.21:A Darlington stage and a common-collector€“common-emitter cascade are shown schematically in Fig. 7.40, where RS
Answer Preview: a In both cases 27 10 3 AV b For the Darlington stage C gs …

, Chapter: 2 -Problem: 6 >> Estimate the series base resistance, series collector resistance rc, base-emitter capacitance, base-collector capacitance, and collector-substrate capacitance of the high-current npn transistor structure shown in Fig. 2.73. This structure is typical of those used as the output transistor in operational amplifiers that must supply up to about 20 mA. Assume a doping profile as shown in Fig. 2.17.Sho
Answer Preview: (a) Series base R: Emitter periphery adjacent to a base contact is: P = 4 40 m = 160 m Distance from …

, Chapter: 10 -Problem: 10 >> Design a voltage-controlled oscillator based on the circuit of Fig. 10.21a. The center frequency is to be 10 kHz, C = 0.01µF, and VCC = 5 V. For the transistors β = 100 and IS= 10ˆ’16A. The frequency is to be varied by 2:1 by an input ˆ† Vin= 200 mV. Specify all resistors and the dc value of Vin. Use SPICE to check your design and also to produce a plot of the transfer characteristic from Vinto f
Answer Preview: = 280 A = 0763 V I 1 = 305 A at center for 2:1 var…

, Chapter: 9 -Problem: 3 >> If an amplifier has a phase margin of 20°, how much does the closed-loop gain peak (above the low frequency value) at the frequency where the loop-gain magnitude is unity?
Answer Preview: T j o 1 T j o 160 But T j o acj …

, Chapter: 3 -Problem: 4 >> For the common-source amplifier of Fig. 3.12, calculate the small-signal voltage gain and the bias values of Viand Voat the edge of the triode region. Also calculate the bias values of Viand Vowhere the small-signal voltage gain is unity with the transistor operating in the active region. What is the maximum voltage gain of this stage? Assume VDD= 3V, RD= 5 k „¦, μnCox= 200 μA/V2, W = 10μm, L =
Answer Preview: V O = V DD R D C ox /2 W/L (V 65 V t ) 2 Triode edge V DS = V GS V t = V O V DS = V DD R D cox /2 …

, Chapter: 9 -Problem: 20 >> (a) Calculate the full-power bandwidth of the circuit of Fig. 9.59.(b) If this circuit is connected in a non-inverting unity-gain feedback loop, sketch the output waveform Vo if Vi is a sinusoid of 10 V amplitude and frequency 45 kHz.Fig. 9.59: Transcribed Image Text: +15 V 1?E () 20 ?? 300 ?? ?? Q2
Answer Preview: (a) f = 212 KHz is the full-power bandwidth (b) V …

, Chapter: 8 -Problem: 1 >> (a) In a feedback amplifier, forward gain ? = 100,000 and feedback factor f = 10?3. Calculate overall gain A and the percentage change in A if a changes by 10 percent.(b) Repeat (a) if f = 0.1.
Answer Preview: a b A…

, Chapter: 4 -Problem: 2 >> Repeat problem 4.1 including the effects of nonzero base currents? Repeat problem 4.1:Determine the output current and output resistance of the bipolar current mirror shown in Fig. 4.55. Find the output current if Vout = 1 V, 5 V, and 30 V. Ignore the effects of nonzero base currents. Compare your answer with a SPICE simulation.Figure 4.55: Circuit for Problem 4.1 Use the high-voltage device param
Answer Preview: Assume (1) All transactions are identical I S1 = I S2 = I S3 = I …

, Chapter: 9 -Problem: 42 >> Calculate the return ratio for the inverting amplifier in Fig. 9.64. Here, the controlled source and C in form a simple op-amp model. Assume av(s) = 1000/[(1 + s/100) (1 + s/106)].(a) Assume the op-amp input capacitance Cin = 0.What is the frequency at which |R (jω)| = 1? How does this frequency compare to the frequency at which |av(jω)| = 1?(b) Find the phase margin for the cases Cin = 0, Cin =
Answer Preview: (a) C in = 0 When S = j = j510 4 , |R(j)| = 1. When S = j = j10 5 , |a v (j) | = …

, Chapter: 12 -Problem: 10 >> Calculate the CM output slew rate dVoc / dt for the op amp in Fig. 12.2. Assume ID5= 200 µA and a 5€“pF capacitor is connected from each op-amp output to ground.Figure 12.2: Transcribed Image Text: Vpp VBIAS M4 ?? Vo2 Vo1 Vi2 M2 M1 Vi1 V eme ?? ??? M5 -Vss
Answer Preview: When M1 M2 ar…

, Chapter: 1 -Problem: 8 >> Derive and sketch the complete small-signal equivalent circuit for a bipolar transistor at IC = 0.2 mA, VCB = 3V, VCS = 4 V. Device parameters are Cje0 = 20 fF, C?0 = 10 fF, Ccs0 = 20 fF, ?0 = 100, ?F= 15 ps, ? = 10?3, rb = 200 ?, rc = 100 ?, rex = 4? , and r? = 5?0ro. Assume ?0 = 0.55 V for all junctions.
Answer Preview: g m = I C / V T = 02 mA / 26 mV = 769 mA/V r o = 1/ hg m …

, Chapter: 9 -Problem: 28 >> The CMOS circuit of Fig. 9.56 is to be used as a high-slew-rate op amp. A load capacitance of CL= 10 pF is connected from Voto ground. Supply voltages are ± 5 V and I1= 20 µA. Devices M1 €“ M4have W = 20 µm and L = 1 µm and devices M5€“ M8have W = 60 µm and L = 1 µm. All other NMOS devices have W = 60 µm and L = 1 µm, and all other PMOS devices have W = 300 µm and L = 1 µm. Device data are μnCox=
Answer Preview: dc bias I D = 20A = I 1 in all devices gain A V = G m R o = 219 A/V = 219 A/V V t3 = |V t6 | V …

, Chapter: 7 -Problem: 48 >> Find an expression for Gm(s) = io(s)/Ï…id(s) for the circuit in Fig. 7.33 and verify the equations for the pole and zero given in Section 7.3.5.Fig. 7.33: Transcribed Image Text: VDD ?? M4 V. ? in- M2, in+ M1 ITAIL -Vss (a) g14 ??3 ? ???Vgs4 is4 i, Vo= 0 ??2V2 ??iV1 Vid V2 Vid V1 (b)
Answer Preview: Ignore all r o s and capacita…

, Chapter: 3 -Problem: 2 >> A CE transistor is to be used in the amplifier of Fig. 3.72 with a source resistance RSand collector resistor RC. First, find the overall small-signal gain vo/vias a function of RS, RC, β0, VA, and the collector current IC. Next, determine the value of dc collector bias current ICthat maximizes the small-signal voltage gain. Explain qualitatively why the gain falls at very high and very low colle
Answer Preview: Av = (r /R S +r ) gm (r o R C ) = (r o R C )/r s + r = (V A …

, Chapter: 10 -Problem: 6 >> A phase-locked loop has a center frequency of 105  rad/s, a KO of 103 rad/V-s, and a KD  of 1 V/rad. There is no other gain in the loop. Determine the loop bandwidth in the first-order loop configuration. Determine the single-pole, loop-filter pole location to give the closed-loop poles located on 45? radials from the origin.
Answer Preview: Loop bandwidth = K V = K O K D …

, Chapter: 7 -Problem: 25 >> An amplifier stage is shown in Fig. 7.41 where bias current IBis adjusted so that VO= 0 V dc. Take VSUPPLY= 10 V.(a) Calculate the low-frequency, small-signal trans-resistance Ï…o/ii and use the zero-value time-constant method to estimate the ˆ’3-dB frequency. Data: npn: β = 100, fT = 500 MHz at IC = 1 mA, Cμ0 = 0.7 pF, Cje = 3 pF (at the bias point), Ccs0 = 2 pF, rb = 0, and VA = 120 V. Assume
Answer Preview: a Q 1 V CB 10 06 94 V V BS 20 06 194 V C 1 764 PF at I C …

, Chapter: 2 -Problem: 8 >> The substrate pnp of Fig. 2.36a is to be used as a test device to monitor epitaxial layer thickness. Assume that the flow of minority carriers across the base is vertical, and that the width of the emitter-base and collector-base depletion layers is negligible. Assume that the epi layer resistivity is known to be 2 Ω-cm by independent measurement. The base-emitter voltage is observed to vary from
Answer Preview: From (2 17), for a pnp transistor Q B = q AD p n i 2 /I c exp (V BE /V T ) For this device, …

, Chapter: 8 -Problem: 21 >> If the 723 voltage regulator is used to realize an output voltage Vo = 10 V with a 1-k? load, calculate the output resistance and the loop gain of the regulator. If a 500-? load is connected to the regulator in place of the 1-k? load, calculate the new value of Vo. Use SPICE to determine the line regulation and load regulation of the circuit. Use I1 = 1 mA, ? = 100, VA = 100 V, Is = 10?15 A, and r
Answer Preview: Output resistance before loop is closed, r oa …

, Chapter: 12 -Problem: 21 >> For the circuit in Problem 12.20 a, the applied source voltage is a single-ended signal with Vs1 = 0.2 V sin (100t) and Vs2 = 0. Assume a CMFB loop forces VOC = 0. What are Vo1 (t), Vo2 (t), Vod (t), and Voc (t)? What are Vi1 (t), Vi2 (t), Vid (t), and Vic (t)?Data from Problem 12.20:(a) R1 = R2 = 1 k? and R3 = R4 = 5 k?.
Answer Preview: V s1 02 sin 100 t V V s2 0 V sd V s1 V s2 02 S…

, Chapter: 1 -Problem: 2 >> Calculate the zero-bias junction capacitance for the example in Problem 1.1, and also calculate the value at 5 V reverse bias and 0.3 V forward bias. Assume a junction area of 2 × 10?5 cm2.Data from Prob. 1.1Calculate the built-in potential, depletion-layer depths, and maximum field in a plane-abrupt pn junction in silicon with doping densities NA = 8 × 1015 atoms/cm3 and ND = 1017 atoms/cm3. Assu
Answer Preview: From (1 20), the zero bias junction capacitance …

, Chapter: 9 -Problem: 31 >> The Miller-compensated two-stage op amp in Fig. 9.25 can be modeled as shown in Fig. 9.26. In the model, let gm1= 0.5 mA/V, R1= 200 kΩ, gm6= 2 mA/V, R2= 100 kΩ, C1= 0.1 pF, and C2= 8 pF.(a) Assume the op amp is connected in negative feedback with f = 0.5. What is the value of C that gives a 45° phase margin? Assume the right half-plane (RHP) zero has been eliminated, and assume the feedback netw
Answer Preview: (a) Similar to problem 9 30, the …

, Chapter: 8 -Problem: 9 >> Repeat Problem 8.7 using the formulas from return-ratio analysis. Repeat Problem 8.7The ac schematic of a shunt-shunt feed-back amplifier is shown in Fig. 8.48. All transistors have ID = 1 mA, W/L = 100, k' = 60 μA/V2, and λ = 1/(50 V). (a) Calculate the overall gain vo/ii, the loop transmission, the input impedance, and the output impedance at low frequencies. Use the formulas from two-port ana
Answer Preview: g m1 r 01 are the same as in Problem 87 a R r 03 R 3 g m1 r 0…

, Chapter: 2 -Problem: 20 >> Determine the direct fabrication cost of an integrated circuit that is 150 mils on a side in size. Assume a wafer-fab cost of $130.00, a package and testing cost of $0.40, a die-fab yield of 0.8, and a final test yield of 0.8. Work the problem for yield curves A,B, andC in Fig. 2.68. Assume a 4-inch wafer. Fig. 2.68 Transc
Answer Preview: Area = (150 mils) 2 = 22,500 mil 2 (a) C…

, Chapter: 9 -Problem: 46 >> Consider a two-stage CMOS op amp modeled by the equivalent circuit in Fig. 9.18, where is = gmvidand vidis the differential op-amp input. Let gm= 19.7mA/V, R1 = R2= 6.67 kΩ, and C1 = C2= C = 2 pF. Calculate and sketch the root locus when feedback is applied as f varies from 0 to 1. Calculate the real component of s for which the poles become complex. Is the amplifier unconditionally stable? If ye
Answer Preview: From (9 32), From (933), From (927a), From rule 6, where 1 gives the positions on the real axis wher…

, Chapter: 12 -Problem: 13 >> Compute the op-amp CM and DM load capacitances for the output loading in Fig. 12.53 a and 12.53 b. Assume the inverting voltage buffers in Fig. 12.53 b are ideal.Figure 12.53 (a): Figure 1253 (b): Transcribed Image Text: Vo1 7 pF 6 pF op amp Vo2 7 pF (a) Vo1 3 pF -1 5 pF 5 pF op amp -1 Vo2 3 pF (b)
Answer Preview: Symmetry or the Miller eff…

, Chapter: 1 -Problem: 17 >> Use the device data of Problems 1.15 and 1.16 to calculate the frequency of unity current gain of this transistor with VDS = 3V, VSB = 0 V, VGS = 1 V, 1.5 V, and 2 V.Data from Prob. 1.16:Derive and sketch the complete small-signal equivalent circuit for the device of Problem 1.15 with VGS = 1 V, VDS = 2 V, and VSB = 1 V. Use ?0 = 0.7 V, Csb0 = Cdb0 = 20 fF, and Cgb = 5 fF. Overlap capacitance from
Answer Preview: From (1 208), From (1 179) Here, 1 + V DS = 1 …

, Chapter: 10 -Problem: 11 >> Using the methods of Section 10.4, design a circuit with a transfer characteristicIo = KI3/2iforIi ?0. The input bias voltage must be?VBE, and the output bias voltage is equal to 2VBE. The value of Io should be 100µA for Ii =100µA. The supply voltage available is VCC = 5 V and device data are? = 100 and IS = 10?17A. Use SPICE to verify your design and then examine the effect of finiterb = 200 and
Answer Preview: V BE1 + V BE6 + V BE5 + V BE4 = V …

, Chapter: 12 -Problem: 23 >> A fully differential op amp with CMFB is shown in Fig. 12.57. For M1, M1C, M2, and M2C, use W/L = (64 µm) / (0.8 µm). For M3 €“ M4, M26 €“ M27and M11, W / L = (96 µm) / (1.4 µm). For M21€“ M24, W / L = (6 µm) / (0.8 µm). For M14, M25, and M52, W / L = (16 µm) / (0.8 µm). For M13, W / L = (1.4 µm) / (0.8 µm). Take VCM = ˆ’0.65 V.(a) Choose W values for M12 and M51 so that |ID13|=20 µA. Use L = 0.8
Answer Preview: a I D51 I D1 I D2 I D13 I D52 100 100 20 100 120 A I D12 I D13 2…

, Chapter: 2 -Problem: 18 >> Show that two MOS transistors connected in series with channel lengths of L1and L2and identical channel widths of W can be modeled as one equivalent MOS transistor whose width is W and whose length is L1+ L2, as shown in Fig. 2.77.Assume the transistors are identical except for their channel lengths. Ignore the body effect and channel-length modulation. Fig. 2.77
Answer Preview: M 2 can operate in active or triode region. M 1 always operates in trio…

, Chapter: 9 -Problem: 34 >> Plot a locus of the poles of (9.27) as C varies from 0 to ?. Use R1 = 200 k?, gm = 2 mA/V, R2 = 100 k?, C1 = 0.1 pF, and C2 = 8 pF.
Answer Preview: The denominator of (9 27) is 1 + 5 (C 2 R 2 + C 1 …

, Chapter: 7 -Problem: 10 >> For the source follower in Fig. 7.13b, find the low-frequency gain and plot the magnitude and phase of its voltage gain versus frequency from f = 10 kHz to f = 20 GHz, using log scales. Compare your plot with a SPICE simulation. Use the transistor data given in Problem 7.2 with a resistive load of 1 kΩ and then a capacitive load of 400 pF. In both cases, take ID= 0.5 mA. Use a 1-mV input pulse am
Answer Preview: 26 10 1…

, Chapter: 4 -Problem: 3 >> Design a simple MOS current mirror of the type show in Fig. 4.4 to meet the following constraints:Figure 4.4: Hypothetical band-gap reference circuit (a) Transistor M2 must operate in the active region for values of VOUT to within 0.2 V of ground.(b) The output current must be 50 µA.(c) The output current must change less than 1 percent for a change in output voltage of 1 V.Make M1 and M2 identic
Answer Preview: From table (2 4), K = n Cox = 450 3 9 8 86 10 14 0 08 10 5 = 1…

, Chapter: 8 -Problem: 28 >> An ac schematic of a local shunt-shunt feedback circuit is shown in Fig. 8.57. Take RF= 100 kΩ and RL= 15 kΩ. For the MOS transistor, ID= 0.5 mA, W/L = 100, k€™ = 180 µA/V2, and ro= ˆž. Calculate input resistance, output resistance, loop transmission, and closed-loop gain:(a) Using the formulas from two-port analysis (Section 8.5).(b) Using the formulas from return-ratio analysis (Section 8.8).F
Answer Preview: (a) = 42 10 3 A/V a = R F (g m ) (R L || R F ) = 100 k 42 m (100 k || 15 k) = 55 …

, Chapter: 12 -Problem: 28 >> Assume that the CMFB circuit in the example in Section 12.6.1 is changed so that the CM-sense amplifier has a low-frequency gain |acms0| = 2.5. Determine the compensation capacitor C needed in the op amp to assure that the CMC and DM feedback loops in the example have a phase margin of 45? or larger.
Answer Preview: For the CMC loop 222 10 12 F 222 …

, Chapter: 9 -Problem: 7 >> Repeat Problem 9.6 for the amplifier of Problem 9.4.Data from Prob. 9.6:The amplifier of Problem 9.5 is to be compensated by reducing the magnitude of the most dominant pole.(a) Calculate the dominant-pole magnitude required for unity-gain compensation with 45° phase margin, and the corresponding bandwidth of the circuit with the feedback applied. Assume that the remaining poles do not move.(b) Re
Answer Preview: (a) Dominant pole = 200 KHZ/40,…

, Chapter: 9 -Problem: 6 >> The amplifier of Problem 9.5 is to be compensated by reducing the magnitude of the most dominant pole.(a) Calculate the dominant-pole magnitude required for unity-gain compensation with 45° phase margin, and the corresponding bandwidth of the circuit with the feedback applied. Assume that the remaining poles do not move.(b) Repeat (a) for compensation in a feedback loop with a closed-loop gain of
Answer Preview: a Dominant pole 2 MHZ5000 400 HZ …

, Chapter: 11 -Problem: 21 >> Neglecting flicker noise, calculate the total equivalent input noise voltage for the MC1553 shown in Figure 8.21a. Use β = 100, rb= 100 Ω and assume a sharp cutoff in the frequency response at 50 MHz. Then calculate the average noise figure of the circuit with a source resistance of 50 Ω.Fig. 8.21a: Transcribed Image Te
Answer Preview: From the basic amplifier of fig 8 21 b For R s = 50 , …

, Chapter: 8 -Problem: 12 >> Repeat Problem 8.11 if the output signal is taken as the voltage at the emitter of Q3. Repeat Problem 8.11The half-circuit of a balanced monolithic series-series triple is shown in Fig. 8.18a. Calculate the input impedance, output impedance, loop gain, and overall gain of the half-circuit at low frequencies using the following data:RE1 = RE2 = 290 RF = 1.9k?RL1 = 10.6k RL2 = 6k?For the transistors
Answer Preview: For the basic amplifier Where V 0 is the voltage at Q 3 emitter f half V 1 V 2 R E1 R …

, Chapter: 9 -Problem: 16 >> The input stages of an op amp are shown in the schematic of Fig. 9.59.(a) Assuming that the frequency response is dominated by a single pole, calculate the frequency where the magnitude of the small-signal voltage gain | Ï…o (jω) /Ï…i (jω) | is unity and also the output slew rate of the amplifier.(b) Sketch the response Vo(t) from 0 to 20 µs for a step input at Vi from ˆ’5 V to +5 V. Assume that
Answer Preview: (a) at high fre…

, Chapter: 9 -Problem: 9 >> An op amp with low-frequency gain of 108 dB has three negative real poles with magnitudes 30 kHz, 500 kHz, and 10 MHz before compensation. The circuit is compensated by placing a capacitance across the second stage, causing the second most dominant pole to become negligible because of pole splitting. Assume the small-signal transconductance of the second stage is 6.39 mA/V and the small-signal res
Answer Preview: Calculate dominant pole freq required When compensate…

, Chapter: 9 -Problem: 23 >> If the circuit of Fig. 9.61 is used to generate the voltage to be applied to the gate of M9in Fig. 9.60, calculate the W/L of M9required to move the right half-plane zero to infinity. Use data from Table 2.1 with Xd= 1 µm. Check your result with SPICE.Figure 9.60: Figure 9.61: Table 2.1: Transcribed Image Text:
Answer Preview: Set R Z = 1/g m6 = 1/194 = 515 k = 194 = k (V GS9 V t ) | VDS = 0 = g m9 …

, Chapter: 8 -Problem: 8 >> (a) Repeat Problem 8.7(a) with all NMOS transistors in Fig. 8.48 replaced by bipolar npn transistors. All collector currents are 1 mA and β = 200,VA = 50 V, and rb=0. (b) If the circuit is fed from a source resistance of1k in parallel with ii, what is the new output resistance of the circuit? Transcribed Image Text:
Answer Preview: a Basic amplifier r 1 r 2 r 3 g m 52K g m 126 r 0 50 k R 1 10k r 1 52 10152 342k R 2 …

, Chapter: 9 -Problem: 15 >> Repeat Problem 9.14 if the circuit has negative real poles with magnitudes 100 Hz and 100 kHz and a negative real zero with magnitude 120 kHz.Data from Prob. 9.14:An op amp has two negative real open-loop poles with magnitudes 100 Hz and 120 kHz and a negative real zero with magnitude 100 kHz. The low frequency open-loop voltage gain of the op amp is 100 dB. If this amplifier is placed in a negati
Answer Preview: Normalize to KHz Break away point ( i + 100) ( i + 120) …

, Chapter: 12 -Problem: 8 >> The op amp in Problem 12.5 is connected in feedback as shown in Fig. 12.32 a. The CMFB is as described in Problem 12.6. Compute the low-frequency closed-loop gains Adm= vod/vsdand Acm = voc/vscif R1 = R2= R3= R4= 100 MΩ.Figure 12.32 (a): Transcribed Image Text: R3 R1 V od Vad R2 R4 (a)
Answer Preview: 0985 For A cm re…

, Chapter: 9 -Problem: 21 >> For the CMOS operational amplifier shown in Fig. 9.60, calculate the open-loop voltage gain, unity gain bandwidth, and slew rate. Assume the parameters of Table 2.1 with Xd= 1 µm. Assume that the gate of M9is connected to the positive power supply and that the W/L of M9has been chosen to cancel the right half-plane zero. Compare your results with a SPICE simulation.Fig. 9.60:Table 2.1:
Answer Preview: L eff = L 2Ld Xd = 8 2(03) 1 = 64 I D = 20 A for m g , m 5 , m 7 , m 6 …

, Chapter: 7 -Problem: 13 >> Repeat Problem 7.12 for a NMOS commongate stage using RL = 0 and RS = ?. Use ID = 0.5 mA and the MOS transistor data in Problem 7.2. Plot the impedance magnitudes from f = 100 kHz to f = 100 GHz.Data from Prob. 7.12:A common-base stage has the following parameters: IC = 0.5 mA, C? = 10 pF, C? = 0.3 pF, rb = 200 ?, ? = 100, ro = ?, RL = 0, and RS = ?.(a) Calculate an expression for the small-signal
Answer Preview: a f 3dB 29…

, Chapter: 11 -Problem: 20 >> (a) Neglecting capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.52 with RS= 5 kΩ. Use data as in Problem 11.10.(b) If the flicker noise corner frequency for each device is 1 kHz, calculate the low frequency where the spot noise figure is 3 dB above the value in (a).Data from Prob. 11.10:The ac schematic of a low-input-impedance common-base amplifier is shown in
Answer Preview: (a) From 11 10, the total input noise current is = 64 10 24 + …

, Chapter: 7 -Problem: 19 >> Repeat Problem 7.18 if a 900 source-degeneration resistor is included in the circuit.Data from Prob. 7.18:Repeat Problem 7.14 using a NMOS transistor in place of the bipolar transistor. Use ID = 0.5mA and the transistor data in Problem 7.2.Data from Prob. 7.14:The ac schematic of a common-emitter stage is shown in Fig. 7.2a. Calculate the low-frequency small-signal voltage gain Ï…o/Ï…i and use the
Answer Preview: 34 V 1 R S R 1 g m 1R S V gs Cgs Rgso 98 10 15 …

, Chapter: 8 -Problem: 24 >> A CMOS feedback amplifier is shown in Fig. 8.53. If the dc input voltage is zero, calculate the overall gain Ï…o/Ï…iand the output resistance. Compare your answer with a SPICE simulation. Use μnCox= 60 × 10ˆ’6A/V2,μpCox= 30 × 10ˆ’6A/V2, Vtn= 0.8 V, Vtp= ˆ’ 0.8 V, λn= |λp| = 0.03 Vˆ’1, and γn= γp= 0.Fig. 8.53: Trans
Answer Preview: I D8 = 200 A = 734 = 693 A/…

, Chapter: 12 -Problem: 24 >> The feedback circuit in Fig. 12.58 is a switched-capacitor circuit during one clock phase. Assume the op amp is the folded-cascode op amp in Fig. 12.31.(a) Calculate the DM and CM output load capacitances, considering only the capacitances in the Fig. 12.58.(b) If the op-amp bias currents are |ID3| = |ID4| = 100 µA and |ID5| = ID11 = ID12 = 200 µA, calculate the DM output slew rate dVod/dt.(c) If
Answer Preview: a b c V ss V ov11 V ov1A V o1 V …

, Chapter: 11 -Problem: 7 >> Four methods of achieving an input impedance greater than 100 kΩ are shown in the ac schematics of Fig. 11.50.(a) Neglecting flicker noise and capacitive effects, derive expressions for the equivalent input noise voltage and current generators of these circuits. For circuit (i) this will be on the source side of the 100-kΩ resistor.(b) Assuming that following stages limit the bandwidth to dc-20
Answer Preview: (a) (i) Short inputs and equate noise V 1 = V i + i i R s Neglecting correlation Open …

, Chapter: 7 -Problem: 43 >> AMOS cascode stage is shown in Fig. 7.43b. Replace the load resistor with a load capacitor CL= 2 pF. Assume the total capacitance that connects to the drain of M1 can be modeled by a capacitor Cp= 0.2pF from that drain to ac ground. Ignore all other capacitors. Therefore, the gain for this circuit has only two poles. For both transistors, take ID= 100 µA, W = 20 µm, Leff= 0.5 µm, k’ = 180 µA
Answer Preview: 12 10 3 AV a With C L open C P r o1 02 10 12 25 10 5 5 10 8 S W…

, Chapter: 9 -Problem: 17 >> Repeat Problem 9.16 if the circuit of Fig. 9.59 is compensated by a capacitor of 0.05 µF connected from the base of Q5to ground. Assume that the voltage gain from the base of Q5to Vois ˆ’500.Data from Prob. 9.16:The input stages of an op amp are shown in the schematic of Fig. 9.59.Assuming that the frequency response is dominated by a single pole, calculate the frequency where the magnitude of the
Answer Preview: Where A = 500…

, Chapter: 9 -Problem: 8 >> An op amp has a low-frequency open-loop voltage gain of 100,000 and a frequency response with a single negative-real pole with magnitude 5 Hz. This amplifier is to be connected in a series-shunt feedback loop with f = 0.01 giving a low-frequency closed-loop voltage gain A0‰ˆ 100. If the output impedance without feedback is resistive with a value of 100 Ω, show that the output impedance of the fee
Answer Preview: a o 100000 1 5 2 radsec From A and B LR …

, Chapter: 8 -Problem: 19 >> Calculate the transconductance, input impedance, output impedance, and loop transmission at low frequencies of the local series-feedback stage of Fig. 8.34 with parameters RE= 200 Ω, β = 150, IC= 1 mA, rb= 200 Ω, and VA= 80 V.Fig. 8.34: Transcribed Image Text: RE (a) &mV1 RE (b) RE Vys = i„Rg (c)
Answer Preview: Transconductance = 437 mA/V Input resis…

, Chapter: 7 -Problem: 12 >> A common-base stage has the following parameters: IC = 0.5 mA, C? = 10 pF, C? = 0.3 pF, rb = 200 ?, ? = 100, ro = ?, RL = 0, and RS = ?.(a) Calculate an expression for the small-signal current gain of the stage as a function of frequency and thus determine the frequency where the current gain is 3 dB below its low-frequency value.(b) Calculate the values of the elements in the small-signal equival
Answer Preview: a b R Z R b …

, Chapter: 9 -Problem: 38 >> The single-stage op amp in Fig. 9.54 has a nondominant pole p2with |p2|=200 Mrad/s. The op amp is in a unity-gain negative feedback loop (f = 1).(a) If gm1 = 0.3 mA/V, what value of CL givesa 45° phase margin? (Assume that the capacitance at the op amp output is dominated by CL and the op-amp gain a(s) can be modeled as having two poles.)(b) If ITAIL = 0.5 mA, what is the output slew rate with thi
Answer Preview: (a) …

, Chapter: 7 -Problem: 11 >> (a) Find expressions for R1, R2, and L in the output impedance model for a MOS source follower assuming RS ? 1/gm, ? ? 0, and ?sb = ?o.(b) Plot the magnitude of the output impedance versus frequency from f = 10 kHz to f = 10 GHz, using log scales, when RS = 1 M, gm = 0.3 mA/V, and ? = 0.
Answer Preview: a Use 767 769 and make the replacements R S R s o C C gs r …

, Chapter: 7 -Problem: 16 >> Repeat Problem 7.14 if a resistor of value 30 kΩ is connected between collector and base of the transistor.Data from Prob. 7.14:The ac schematic of a common-emitter stage is shown in Fig. 7.2a. Calculate the low-frequency small-signal voltage gain Ï…o/Ï…i and use the zerovalue time-constant method to estimate the ˆ’3-dB frequency for RS = 10 kΩ and RL = 5 kΩ. Data: β = 200, fT = 600 MHz (at IC
Answer Preview: R 1 || r = 181 || 52 k = 175 R o = R S || r || R 1 = 10 k || 52 k || 181 …

, Chapter: 11 -Problem: 23 >> Repeat Problem 11.22 if the MOS transistors in Fig. 8.48 are replaced by bipolar transistors. Assume that β = 200, rb= 300, IC= 1 mA and the flicker noise corner frequency is fa= 5 kHz. Neglect capacitive effects.Data from Prob. 11.22:Calculate the total equivalent input noise current for the shunt-shunt feedback circuit of Fig. 8.48 in a bandwidth from 0.01 Hz to 100 kHz. Use the MOS transistor
Answer Preview: = 46 10 19 A 2 i iT = 067 nA …

, Chapter: 11 -Problem: 25 >> A MOS current source of the type shown in Fig. 4.4 is to be designed to achieve minimum output current noise. The two transistors must be identical and the total gate area of the two transistors combined must not exceed 10 µm2. Choose the W and Lof the devices under two different assumptions:(a) 1/f noise dominates.(b) Thermal noise dominates.Assume that Ld and Xd are zero. The minimum allowed tra
Answer Preview: (a) Maximize L to minimize 1/f noise W 1 = 06 m …

, Chapter: 9 -Problem: 36 >> For the three-stage op amp with nested Miller compensation in Fig. 9.30c, determine the values of the compensation capacitors that give a 60—¦ phase margin when the op amp is in a unity-gain negative feedback loop (f=1). Assume that the zeros due to feed forward have been eliminated. Design for complex poles p2and p3. Use R0= R1= R2= 5 kΩ, C0= C1= 0.5 pF, and C2= 6 pF. Use gm0= gm1and gm2 = 6gm1.
Answer Preview: Assume |P 2 | >> |P 1 |. At unity, P 1 contribut…

, Chapter: 9 -Problem: 13 >> For the circuit of Fig. 9.41, parameter values are RF= 5 kΩ, RE= 50 Ω, and CF= 1.5 pF. The basic amplifier of the circuit is shown in Fig. 9.42 and has two negative real poles with magnitudes 3 MHz and 6 MHz. The low-frequency current gain of the basic amplifier is 4000. Assuming that the loop gain of the circuit of Fig. 9.41 can be varied without changing the parameters of the basic amplifier,
Answer Preview: Zero freq. Z = 1/R F C F = 1/50001510 12 = 133 10 8 …

, Chapter: 10 -Problem: 7 >> For the same PLL of Problem 10.6, design a loop filter with a zero that gives a crossover frequency for the loop gain of 100 rad/s. The loop phase shift at the loop crossover frequency should be ?135?.
Answer Preview: If w 2 (the zero frequency) is at the unity gain point, then the loop phase shif…

, Chapter: 10 -Problem: 2 >> For the emitter-coupled pair of Fig. 10.1, determine the magnitude of the dc differential input voltage required to cause the slope of the transfer curve to be different by 1 percent from the slope through the origin.Fig. 10.1 Transcribed Image Text: 12 Q2 Vid EE
Answer Preview: For the emitter coupled pair The slope of t…

, Chapter: 9 -Problem: 32 >> Repeat Problem 9.31(a) for the common-gate compensation scheme in Fig. 9.22 a.Data from Prob. 9.31 (a):The Miller-compensated two-stage op amp in Fig. 9.25 can be modeled as shown in Fig. 9.26. In the model, let gm1 = 0.5 mA/V, R1 = 200 kΩ, gm6 = 2 mA/V, R2 = 100 kΩ, C1 = 0.1 pF, and C2 = 8 pF.(a) Assume the op amp is connected in negative feedback with f = 0.5. What is the value of C that gives
Answer Preview: Similar to Problem 931 a, A …

, Chapter: 11 -Problem: 10 >> The ac schematic of a low-input-impedance common-base amplifier is shown in Fig. 11.52.(a) Calculate the equivalent noise voltage and current generators of this circuit at the emitter of Q1 using IC1 = IC2 = 1 mA, rb1 = rb2 = 0, β1 = β2 = 100, fT1 = fT2 = 400 MHz. Neglect flicker noise but include capacitive effects in the transistors. Use SPICE to check your result.(b) If RS = 5 kΩ, and later
Answer Preview: (a) Represent total noise by Open circuit input and eguate output noise, …

, Chapter: 9 -Problem: 26 >> Repeat Problem 9.25 except, for the op amp, use the aspect ratios, supply voltages, and bias current given in Fig. 6.58 instead of the values in Fig. 9.60. Also, for the bias circuit, use the aspect ratios, supply voltages, and bias current given in Problem 9.24. Ignore junction capacitance for all transistors. Also, assume that Xd= 0.1 µm for all transistors operating in the active region, and us
Answer Preview: To obtain 45 phase margin, set the 2 nd pole to funity = 328 M ra…

, Chapter: 10 -Problem: 12 >> Show that the CMOS circuit of Fig. 10.25 realizes a square-law transfer characteristic from Vito Io assuming that the MOSFETs have square-law characteristics. Specify the range of Viover which this holds. (The bias analysis of Section 9.6.4 applies.) All PMOS devices have W/L=60 and all NMOS haveW/L=20. Device data are μnCox= 60µA/V2, μpCox=20µA/V2, Vtn=0.7V, Vtp= ˆ’0.7V, γ = 0, and λ= 0.Use S
Answer Preview: I D1 = I D2 = I D3 = I D4 = 50 A I D5 = I D6 = I D7 = I D8 = 50 A I D9 = I D10 = 100 A for m 1 thru …

, Chapter: 8 -Problem: 29 >> Replace the MOS transistor in Fig. 8.57 by a npn transistor. Take RF= 2 kΩ, RL= 2 kΩ, β = 200, IC= 1 mA, rb= 0, and VA = 100 V.(a) Repeat Problem 8.28(a).(b) Repeat Problem 8.28(b).Data from Prob. 8.28 (a):(a) Using the formulas from two-port analysis (Section 8.5).Data from Prob. 8.28 (b):(b) Using the formulas from return-ratio analysis (Section 8.8).Fig. 8.57:
Answer Preview: (a) a = (r || R F ) (g m ) (r o || R L || R F ) = (52 k || 2 k) 0038 (100 k || 2 k || 2 k) = 54 10 …

, Chapter: 7 -Problem: 9 >> Calculate the values of the elements in the small-signal equivalent circuits for the input and output impedances of the emitter follower of Problem 7.8. Sketch the magnitudes of these impedances as a function of frequency from f = 10 kHz to f = 20 MHz, using log scales. Use SPICE to determine the small-signal step response of the circuit for a resistive load of 1 k? and then a capacitive load of 4
Answer Preview: 204 k R 2 …

, Chapter: 11 -Problem: 27 >> Use SPICE to verify the noise analysis of the NE5234 op amp given in Section 11.8. Then add flicker noise generators assuming a = 1 in (11.13) and the transistor flicker noise corner frequency is 1 kHz. Which device dominates the noise performance at 1 Hz?
Answer Preview: NE5234 OP AMP, CASE 1: INPUT NOISE VOLTAGE WITHOUT FLICKER NOISE POWER SUPPLIES VCC VEE VCC VEE BIAS CIRCUIT Q47 47 Q48 48 Q49 48 Q50 50 Q51 VEE Q52 VCC Q53 Q54 Q55 Q56 Q57 56 Q58 58 Q59 58 Q60 60 VEE …

, Chapter: 7 -Problem: 31 >> An amplifier stage is shown in Fig. 7.44.(a) Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…i.(b) Apply the zero-value time-constant method to the DM half-circuit to calculate the ˆ’3-dB frequency of the gain. Data: Ccs0 = 2 pF, Cμ0 = 0.5 pF, Cje = 4 pF (at the bias point), fT = 500 MHz (at IC = 2 mA), β = 200, rb = 0, and ro = ˆž. Assume n = 0.5 and ψ0 = 0.55 V for all junctions.
Answer Preview: a Halfcircuit3 Q 1 I a 10 I b2 125 A 245 pF at 2 mA C b1 204 …

, Chapter: 8 -Problem: 34 >> (a) Calculate the loop gain T = af for the series-shunt feedback circuit in Fig. 8.59 using hparameter two-ports. Take R1= 200 kΩ, and R2= 100 kΩ. For the op amp, assume Ri= 50 kΩ, Ro= 1 MΩ, and av= 1 × 103.(b) If the input source location and type in Fig. 8.59 are changed as shown in Fig. 8.61, the feedback is now shunt-shunt. Calculate the loop gain T = af for this shunt-shunt feedback circ
Answer Preview: (a) Z i = h||a + h||f = 50 k + 67 k = 117 k y o = h22a + h22…

, Chapter: 12 -Problem: 33 >> For the op amp in Fig. 12.40, what are the output voltage swing limits of Vo1 and Vo2if the thresh-old voltages of only M1A, M2A, M3A, and M4Aare changed toVt1A= Vt2A= ˆ’0.3 V and Vt3A= Vt4A= 0.3V?Figure 12.40: Transcribed Image Text: VpD M12 M11 BiasB M2A M1A BiasC Vo2 Vo1 M2 V1 M1 M4A ??? BiasD Bi
Answer Preview: The circuit is balanced so the swing limits are the same for V o1 and V o2 The up…

, Chapter: 10 -Problem: 1 >> Sketch the dc transfer curve Iout versus V2 for the Gilbert multiplier of Fig. 10.4 for V1 equal to 0.1VT , 0.5VT , and VT .
Answer Preview: The multiplier transfer function is I OUT = I C 3 5 I C 4 6 = I EE ta…

, Chapter: 12 -Problem: 15 >> A differential amplifier with local CMFB is shown in Fig. 12.54. Use |Vov| = 0.2 V for all transistors, Vtn= ˆ’Vtp= 0.6 V, ID5= 200 µA, VAn= 10 V, |VAp| = 20 V, and γ = 0. Assume VDD= VSS= 2.5V and Vic= 0.(a) What is the dc common-mode output voltage of this amplifier?(b) Compute the low-frequency gains adm and acm. Compare these gains with the gains calculated in the first example in Section 12.
Answer Preview: a V oc V G3 V DD V tp V ov3 25 06 02 17 V b a dm g m1 r o1 r o3 20 …

, Chapter: 10 -Problem: 8 >> Estimate the capture range of the PLL of Problem 10.7, assuming that it is not artificially limited by the VCO frequency range.
Answer Preview: For ca…

, Chapter: 7 -Problem: 27 >> A differential circuit employing active loads is shown in Fig. 7.42. Bias voltage VBis adjusted so that the collectors of Q1and Q2are at +5 V dc. Biasing resistors are RB1= 10 kΩ and RB2= 20 kΩ. Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…i, and use the zero-value time-constant method in the DM half-circuit to estimate the ˆ’3-dB frequency of the DM gain. Use the device data in
Answer Preview: Halfcircuits ac Equivalent 10 A I C1 I C3 I C5 2 5 A Q 1 122 pF at 1 mA C 1 12 pF at 1 m…

, Chapter: 11 -Problem: 18 >> (a) Neglecting flicker noise and capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.54 with RS = 50 ?.(b) If RS were made equal to (i) 100 ? or (ii) 200 k?, would the noise figure increase or decrease? Explain.(c) If RS = 200 k?, and each device has a flicker noise corner frequency of 10 kHz, calculate the low frequency where the circuit spot noise figure is 20 dB
Answer Preview: (a) Equivalent input noise generators for the differential pair = 324 10 17 V 2 /Hz From …

, Chapter: 7 -Problem: 39 >> For the BiCMOS circuit of Fig. 3.78, use the zero-value time-constant method to estimate the first and second most dominant poles of the circuit. Assume an input voltage drive. Use bipolar transistor data from Fig. 2.32 and MOSFET parameters Cgd= 90 fF, Csb= Cdb= 200 fF, and Cgs= 200 fF at the bias point. Further assume μnCox= 40 µA/V2, Vt= 0.8 V, λ = 0, and γ = 0. Use SPICE to check your resul
Answer Preview: I C1 261 A V C1 5261 239 V b1 V GS2 V BE2 147 08 227 V …

, Chapter: 7 -Problem: 29 >> The ac schematics of a common-source stage and a common-source€“common-gate (cascode) stage are shown in Fig. 7.43 with RS= 10 kΩ and RL= 20 kΩ. Using the transistor and operating-point data in Problem 7.2:(a) Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…i for each circuit.(b) Use the zero-value time-constant method to calculate and compare the ˆ’3-dB frequencies of the gain of t
Answer Preview: = 19 10 3 A/V = 89 fF C gd = WL d C ox = 100 02 07 = 14 fF (a) (b) The CS Stage C gs1 R S = 8…

, Chapter: 7 -Problem: 7 >> A MOS differential amplifier is shown in Fig. 7.9. For this circuit, carry out the calculations in Problem 7.6. Use ISS= 1 mA, the values of RT= 300 kΩ and CT= 2 pF as defined in Fig. 7.11b, and the transistor data in Problem 7.2.Fig. 7.9: Fig. 7.11 b: Transcribed Image Text: VDD RL RL Rs V? Rs Iss
Answer Preview: 5 10 3 1 6 10 7 S …

, Chapter: 12 -Problem: 1 >> What are the swing limits for each output of the differential amplifier in Fig. 12.2? Use |Vov| = 0.2 V for all transistors and Vtn= ˆ’Vtp= 0.6 V. Assume VDD= VSS= 2.5 V, Vic= 0 and γ = 0. Also, assume that the common-mode feedback circuit does not limit the output swing. What value of VOCgives the largest symmetric differential output swing? What is the peak value of Vodin this case?Fig. 12.2:
Answer Preview: v ic v tn1 < v o1 < V DD |V ov3 | 0 06 < V …

, Chapter: 9 -Problem: 18 >> The slew rate of the circuit of Fig. 9.59 is to be increased by using 10 kΩ resistors in the emitters Q1and Q2. If the same unity-gain frequency is to be achieved, calculate the new value of compensation capacitor required and the improvement in slew rate. Check your result with SPICE simulations.Fig. 9.59: Transcribed Im
Answer Preview: For same unity gain freq. …

, Chapter: 9 -Problem: 43 >> A technique that allows the return ratio to be simulated using SPICE without disrupting the dc operating point is shown in Fig. 8.60 and explained in Problem 8.33.(a) Use that technique to simulate the return ratio for the op amp from Problem 9.21 connected in a non-inverting unity-gain configuration for f = 1 kHz, 100 kHz, 10 MHz, and 1 GHz.(b) Use that technique to plot the magnitude and phase o
Answer Preview: (a) (b) The unity gain frequency is 4 MHz The phase margin is 70. The gain margins is 10dB. RETURN R…

, Chapter: 9 -Problem: 30 >> Determine the compensation capacitor for the two-stage op amp in the example in Section 9.4.3 that gives a 60° phase margin.
Answer Preview: Assume the zero has been eliminated and |P 3 ||P 2 ||P 1 |, at the op…

, Chapter: 8 -Problem: 31 >> Replace the MOS transistor in Fig. 8.58 with a npn transistor. For the transistor, IC= 0.5 mA and ro= ˆž.(a) Repeat the calculations in Problem 8.30(a).(b) Repeat the calculations in Problem 8.30(b).Fig. 8.58: Transcribed Image Text: V DD V? V.
Answer Preview: (a) The basic amplifier without the feedback signal inserted at the inverting in…

, Chapter: 9 -Problem: 40 >> Calculate the return ratio for the feedback circuit in Fig. 9.62. Assume that the amplifier voltage gain is constant with av> 0. Show that this feedback circuit is always stable if each impedance is either a resistor or a capacitor.Figure 9·62: Transcribed Image Text: Z2 Z, Vx V.
Answer Preview: There are 4 possibilitie…

, Chapter: 6 -Problem: 1 >> For the circuit of Fig. 6.53, determine the output current as a function of the input voltage. Assume that the transistor operates in the active region.Figure 6.53 Transcribed Image Text: lout Ideal Vin
Answer Preview: For ideal opa…

, Chapter: 4 -Problem: 6 >> Using the data given in the example of Section 1.9, include the effects of substrate leakage in the calculation of the output resistance for the circuit of Problem 4.5. Let VOUT= 2Vand 3V?Data from 4.5Calculate the output resistance of the circuit of Fig. 4.9, assuming that IIN =100 µA and the devices have drawn dimensions of 100 µm/1 µm. Use the process parameters given in Table 2.4, and assum
Answer Preview: Look at M 2 V DS M2 = V OUT V DS M1 = V OUT V GS M1 V GS M1 = V t + 2I D …

, Chapter: 6 -Problem: 27 >> Determine the small-signal voltage gain of the NE5234 if all the values of all the resistors in the input stage are doubled. Assume the common-mode input voltage is low enough that Q1 and Q2 are off. Assume the output stage is biased as described in this chapter.
Answer Preview: Doubling the resistance of all the resistors in the input stage gives R 6 = R 7 = 20 k R 8 = R 13 = …

, Chapter: 6 -Problem: 16 >> Calculate the common-mode input range of the op amp in Fig. 6.25. Assume that all the transistors are enhancement-mode devices with |Vt| = 1V,and ignore the body effect. Also assume that the biasing is arranged so that |Vov|=0.2 V for each transistor except M9. Finally, assume that M1and M2are biased at the edge of the active region by M9and IC. Figure 6.25
Answer Preview: For all transistors except M9, Vt = 1V and V0V = 0 2V To operate M5 in th…

, Chapter: 4 -Problem: 16 >> Determine the unloaded voltage gain νo/νiand output resistance for the circuit of Fig. 4.59. Neglect rμ. Verify with SPICE and also use SPICE to plot the large-signal VO-VItransfer characteristic for VSUP= 2.5V.Figure 4.59: Transcribed Image Text: +VSUP Os Vo+v• Q4 1.3 V Q2 V = V? + V? ITAIL -VSU
Answer Preview: Half circuit of the dotted box: Is the CE CB configuration: the equivalent circuit is Where R …

, Chapter: 4 -Problem: 27 >> In the analysis of the hypothetical reference of Fig. 4.44, the current I1was assumed proportional to temperature. Assume instead that this current is derived from a diffused resistor, and thus has a TCFof ˆ’1500 ppm/ °C. Determine the new value of VOUTrequired to achieve zero TCFat 25°C. Neglect base current.Fig. 4.44: Tr
Answer Preview: From (4245), Put I 1 = I o [1 K 1 (T T o )] where K 1 = 1500 10 6 V BE(…

, Chapter: 6 -Problem: 6 >> Consider the differential amplifier shown in Fig. 6.4. Choose values of R1and R2for which the gain is equal toˆ’10 and the magnitude of the dc output voltage is less than or equal toˆ’10 mV with V1= V2= 0. Assume that the op amp is ideal except that |IOS|=100 nA.Figure 6.4 Transcribed Image Text: 12
Answer Preview: With V 1 = V 2 = 0 (1) V X = -I B1 (R 1 || R 2 ) = …

, Chapter: 6 -Problem: 12 >> (a) Equation 6.69 gives the random input off-set voltage of the op amp in Fig. 6.16. Explain the polarity of each term in (6.69) by assuming that the matching is perfect except for the term under consideration. Keep in mind that the overdrive is negative for p-channel transistors. Therefore, (6.69) predicts that the offset stemming from W3>W4is negative.(b) Repeat (a) for an op amp that uses an n-
Answer Preview: (a) For simplicity, replace M 5 in fig (6 16) with an ideal current source. Although this change makes the common mode gain of the on amp zero, this change does not affect the characteristics of the c…

, Chapter: 6 -Problem: 24 >> (a)Figure 6.60a shows a folded version of the op amp in Fig. 6.15. A differential inter stage level-shifting network composed of voltage sources V  has been inserted between the first and second stages. Assume that current source I1is implemented using an n-channel transistor with overdrive of Vovn, which is equal to the overdrives of the other n-channel transistors shown in Fig. 6.60a. Assume tha
Answer Preview: (a) CM input range: To keep the transistor that forms I 1 in the active region, V IC > - V SS + V ov…

, Chapter: 4 -Problem: 19 >> Although Gm [cm] of a differential pair with a current-mirror load can be calculated exactly from a small-signal diagram where mismatch is allowed, the calculation is complicated because the mismatch terms interact, and the results are difficult to inter-pret. In practice, the mismatch terms are often a small fraction of the corresponding average values, and the interactions between mismatch terms
Answer Preview: (a) V 1 = (i 1 + i 2 ) r tail i 1 = i 2 (1 d) (b) First sup…

, Chapter: 6 -Problem: 30 >> Repeat Problem 6.29 except replace each pnp transistor with a p-channel MOS transistor and replace each npn transistor with an n-channel MOS transistor. Assume Vt= 0.5 V and Vov= 0.1 V for all n-channel MOS transistors. Also, assume Vt= ˆ’ 0.5 V and Vov= ˆ’ 0.1 V for all p-channel MOS transistors.Data from Prob. 6.29:In Fig. 6.31b, resistive loads were used to extend the common-mode input range to
Answer Preview: The upper end of the common-mode range is limited by M 5 entering the tiode region. With a pure comm…

, Chapter: 7 -Problem: 3 >> Calculate an expression for the output impedance of the circuit in Problem 7.1 as seen by RL and form an equivalent circuit. Plot the magnitude of this impedance on log scales from f = 1 kHz to f = 100 MHz.Circuit in Prob. 7.1: Transcribed Image Text: RL Vo Rs Vi ??
Answer Preview: R = (R S + r b …

, Chapter: 4 -Problem: 24 >> Design the MOS peaking current source in Fig. 4.34 so that IOUT= 0.1 µA.(a) First, let IIN = 1 µA and find the required value of R.(b) Second, let R = 10 kΩ and find the required IIN.In both cases, assume that both transistors are identical and operate in weak inversion with It = 0.1 µA and n = 1.5. Also, find the minimum W/L in both cases, assuming that VGS ˆ’ Vt < 0 is required to operate a tra
Answer Preview: (a) I OUT = 01 A when I 1N = 1 A To keep t…

, Chapter: 4 -Problem: 26 >> Determine the value of sensitivity S of output current to supply voltage for the circuit of Fig. 4.62, where S = (VCC/IOUT)(ˆ‚IOUT/ˆ‚VCC).Fig. 4.62: Transcribed Image Text: Vcc= 15 V |IOUT 10 k2 R1 Q2 1 k2 R2
Answer Preview: For this circuit and I…

, Chapter: 5 -Problem: 11 >> For the circuit of Fig. 5.10, assume that VCC= 12 V, RL= 1 kΩ, and VCE(sat)= 0.2 V. Assume that there is sufficient sinusoidal input voltage available at Vito drive Voto its limits of clipping. Calculate the maximum average power that can be delivered to RLbefore clipping occurs, the corresponding efficiency, and the maximum instantaneous device dissipation. Neglect crossover distortion.Fig. 5.10
Answer Preview: V o = V CC V CE(Sat). = 118 V Supply power = P supply …

, Chapter: 4 -Problem: 18 >> Find Gm[dm] of a source-coupled pair with a current-mirror load with nonzero mismatch (Fig. 4.29b) and show that it is approximately given by (4.184). Calculate the value of Gm[dm] using the following data: Compare your answer with a SPICE simulation. Also, compare your answer to the result that would apply without mismatch?Figure 4.29b:
Answer Preview: i 1 = gm 1 ( Id /2 s ) i 2 = gm 2 ( Id /2 s ) s = (i 1 + i 2 )r tail (1) s [1 + …

, Chapter: 4 -Problem: 34 >> Calculate the bias current of the circuit shown in Fig. 4.65 as a function of R, μnCox, (W/L)1, and (W/L)2. Comment on the temperature behavior of the bias current. For simplicity, assume that Xd= Ld= 0 and ignore the body effect. Assume M4is identical to M3.Fig. 4.65: Transcribed Image Text: VDD M
Answer Preview: Since M 3 = M 4 , |I D3 | = |I D4 | = I D1 = I D2 = I BIAS I BIAS …

, Chapter: 4 -Problem: 20 >> Design a Widlar current source using npn transistors that produces a 5 µA output current. UseFig. 4.31a with identical transistors, VCC = 30 V, and R1 = 30 kΩ. Find the output resistance.Fig. 4.31 a: Transcribed Image Text: Vcc IN | IOUT R1 Ic?! Q2 Q1 R2
Answer Preview: V BE1 = V BE2 + I o …

, Chapter: 4 -Problem: 8 >> For the circuit of Fig. 4.56, assume that (W/L)8= (W/L). Ignoring the body effect, find (W/L)6and (W/L)7so that VDS6 = VDS7= Vov8. Draw the schematic of a double-cascode current mirror that uses the circuit of Fig. 4.56 to bias both cascade devices in the output branch. For this current mirror, calculate the output resistance, the minimum output voltage for which all three transistors in the outpu
Answer Preview: M 8 operate in active region M 6 and M 7 operate in triode region. I = K/2 (W/L) 8 (V GS8 V t ) 2 I …

, Chapter: 4 -Problem: 29 >> A band-gap reference like that of Fig. 4.47 is designed to have nominally zero TCFat 25°C. Due to process variations, the saturation current ISof the transistors is actually twice the nominal value. Assume VOS= 0. What is dVOUT/dT at 25 °C? Neglect base currents.Fig. 4.47: Transcribed Image Text: Vo
Answer Preview: (because base current is ignored) Now double I S1 and I S2 . V …

, Chapter: 6 -Problem: 5 >> Once the offset voltage of the differential amplifier in Problem 6.4 is adjusted to zero, the input-referred offset voltage must remain less than 1 mV in magnitude for common-mode input voltages between ± 10 V. What is the minimum CMRR allowable for the amplifier to meet this requirement?Problem 6.4The differential instrumentation amplifier shown in Fig. 6.56 must have a voltage gain of 103 with a
Answer Preview: CMRR = (V os /V ic ) …

, Chapter: 5 -Problem: 23 >> For the circuit in Fig. 5.34, assume that the input voltage Viis high enough that M1operates in the active region but M2is cut off. Using the same assumptions as in the derivation of (5.116), show that Vois related to Viby the following expression Figure 5.34: Transcribed Image Text: Voy Vosp + V. =
Answer Preview: Assume M 2 = off KCL I d1 = …

, Chapter: 5 -Problem: 24 >> Using a circuit that is the complement of the one in Fig. 5.35, draw the schematic for the bottom error amplifier and output transistor M2, which are shown in block diagram form in Fig. 5.32. In the error amplifier, label the transistors as M21-M27, where M21is the complement of M11, M22is the complement of M12, etc. Also, label the current sources complementary to IBIASand ITAILas IBIASPand ITAIL
Answer Preview: IBIASP M5 …

, Chapter: 5 -Problem: 22 >> Design a CMOS output stage based on the circuit of Fig. 5.31 to deliver ±1 V before clipping at Vowith RL = 1 kΩ  and VDD= VSS= 2.5 V. Use 10 µA bias current in M3and 100 µA idling current in M1and M2. Set (W/L)3= 50/1 and (W/L)6= 25/1. Specify the W/L for M1-M6that minimizes the total chip area. Use the transistor parameters in Table 2.3 except assume that Leff= Ldrwnfor simplicity. The minimum
Answer Preview: = 008 2 fn = 650 mV 2 fp = 750 mV Table (23) K n = 127 A/V; K P = 58 A/V V tn = …

, Chapter: 6 -Problem: 20 >> Design a CMOS op amp based on the folded-cascode architecture of Fig. 6.28 using supply voltages of ± 1.5 V. Use the bias circuit of Fig. 4.42 (with M3and M4cascoded) to generate the bias current IBIAS. Then design an extension to this bias circuit that produces the bias voltagesVBIAS1, VBIAS2, and VBIAS3 based on IBIAS. The output current-drive capability is to be ± 100 μA, the output voltage-
Answer Preview: For I 0(max) = 100 A I D11 = I D12 = 100 A Then half of I D11 should come from M 1 and the other hal…

, Chapter: 4 -Problem: 14 >> Repeat Problem 4.12 except replace Q1and Q2with n-channel MOS transistors M1and M2. Also, replace Q3and Q4with p-channel MOS transistors M3and M4. Assume Wn= 50[1]m and Wp= 100 µm. Repeat Problem 4.12:Determine the unloaded voltage gain νo/νi and output resistance for the circuit of Fig. 4.58. Check with SPICE and also use SPICE to plot out the large-signal VO-VI transfer characteristic for VSUP
Answer Preview: In the figure below, I 1 = I 2 = I 3 = I 4 = 50 A And R O = r 02 || r 04 From (1 163), V An = L eff …

, Chapter: 6 -Problem: 32 >> Find the minimum value of VCC for proper operation of the NE5234 op amp. For simplicity, assume VEE= 0, |VBE(on)| = 0.7 V, and |VCE(sat)| = 0.1 V. Also, ignore base currents. Assume the bias circuits in Figures 6.34 and 6.40 operate properly even though some transistors in these circuits may operate in or near saturation with low VCC.Figure 6.34:
Answer Preview: On possible critical path is from V CC through the emitter-base junctions of Q 74 and Q 65 to the co…

, Chapter: 6 -Problem: 10 >> Calculate the low-frequency PSRR from the Vdd andVss power supplies for the common-source amplifier shown in Fig. 6.57. Assume the transistor is biased in the active region.Figure 6.57 Transcribed Image Text: VDD + Vdd ER Vo Vi Vss + Vss
Answer Preview: v o /v i = - g m …

, Chapter: 4 -Problem: 23 >> Design a MOS Widlar current source using the circuit shown in Fig. 4.31b to meet the following constraints with VDD= 3 V:(a) The input current should be 100 µA, and the output current should be 10 µA.(b) Vov1 = 0.2 V.(c) Transistor M2 must operate in the active region if the voltage from the drain of M2 to ground is at least 0.2 V.(d) The output resistance should be 50 MΩ.Ignore the body effect.
Answer Preview: Ignore BE/X d = L d = 0 R o = r o2 (1 + g m2 R 2 …

, Chapter: 6 -Problem: 14 >> List and explain at least three reasons to select a two-stage op amp with an n-channel input pair instead of with a p-channel input pair for a given application.
Answer Preview: With an n-channel input pair (1) The input-referred offset voltage resulting from …

, Chapter: 4 -Problem: 5 >> Calculate the output resistance of the circuit of Fig. 4.9, assuming that IIN=100 µA and the devices have drawn dimensions of 100 µm/1 µm. Use the process parameters given in Table 2.4, and assume for all devices that Xd= 0. Also, ignore the body effect for simplicity. Compare your answer with a SPICE simulation and also use SPICE to plot the IOUT-VOUTcharacteristic for VOUTfrom 0 to 3 V?Figure
Answer Preview: L eff = 1m 2 (0 09 m) = 0 82 m R 0 = 1/ ID where = dxd/dV DS /L eff = 0 02/0 82 = 0 024 V 1 r 0 = 1/…

, Chapter: 5 -Problem: 21 >> Find the minimum output voltage for the circuit in Fig. 5.31.Figure: 5.31: Transcribed Image Text: VDp BIAS M? M4 M4 RL M2 M5 M6 +o -Vss
Answer Preview: The negative limit on V o is reached when M 6 …

, Chapter: 6 -Problem: 21 >> Draw the schematic of a folded-cascode op amp similar to the op amp in Fig. 6.28 except with two layers of both n- and p-type cascodes. Choose a current mirror that maximizes the output swing. Assume that all transistors have equal overdrive magnitudes except where changes are needed to maximize the output swing. Use the models in Table 2.4 and ignore the body effect. Specify the W/L ratios in mul
Answer Preview: From table (2 4), n = 4 p. Therefore, the produce over drives with equal magn…

, Chapter: 5 -Problem: 15 >> For the output stage of Fig. 5.20a, assume that VCC= 15 V, βF(pnp) = 50, βF(npn) = 200, and for all devices VBE(on)= 0.7 V, VCE(sat)= 0.2 V, IS= 10ˆ’14A. Assume that the magnitude of the collector current in Q13Ais 0.2 mA.(a) Calculate the maximum positive and negative limits of Vo for RL = 10 kΩ, RL = 1 kΩ, and RL = 200 Ω.(b) Calculate the maximum average power that can be delivered to RL =

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8 Reviews for Analysis and Design of Analog Integrated Circuits Textbook Questions And Answers